The present invention relates in general to semiconductor memories, and in particular to an improved flash memory circuit and method of manufacture.
FIG. 1 shows a schematic cross-section of an example of a single-transistor double poly stacked gate flash cell. The cell includes a floating gate 100 made of a first polysilicon layer (poly-1), a control gate 102 made of a second polysilicon layer (poly-2), an N+ drain region 106 and an N++ source region 104 inside a P-well region 108. A thin layer of silicon dioxide of approximately 70 to 120 Angstroms forms the tunnel oxide 110 between the floating gate poly-1 and the channel, and a 150 to 300 Angstroms thick film made of an oxide-nitride-oxide (ONO) sandwich 112 separates the two poly gates 100 and 102.
This cell is programmed by grounding the source terminal, applying a 5 to 10 volt signal to the drain terminal or the bit line (V.sub.BL =5v), and applying a high programming voltage V.sub.PP of, for example, 18 to 20 volts to control gate 102 (V.sub.CG =V.sub.PP). The high voltage on V.sub.CG creates a high electric filed across tunnel oxide 110 generating hot electrons in the channel with enough energy to cross the tunnel oxide. These hot electrons are then trapped in the floating gate poly-1 layer 100 resulting in a higher threshold voltage for the transistor. The cell is thus programmed into an OFF (non-conducting) state.
Erasing of the cell is performed by grounding the control gate and the drain terminal and applying V.sub.PP to the source terminal. The large gate to source voltage causes the trapped electrons on the floating poly 100 to tunnel through the thin oxide layer 110 by a mechanism known as Fowler-Nordhiem. The electrons are collected by the source region 104.
The flash memory cell shown in FIG. 1, however, suffers from a number of drawbacks in terms of its overall performance. Because the source region 104 is subject to very high erase voltages (V.sub.PP), this cell requires a carefully engineered high-voltage junction process. As shown in FIG. 1, the source region 104 is made deeper than the drain region 106 and has a higher doping concentration. The high-voltage junction requirement results in a more complex and therefore more expensive process. Further, the high-voltage junction requirement results in a cell that is not scaleable. That is, the high-voltage diffusion to high-voltage diffusion spacing requirements increases the cell layout pitch. Lower endurance is another drawback of the high-voltage junction. since under high voltage conditions, the source region 104 cannot withstand a large number of erasures.
Furthermore, applying the high V.sub.PP voltage to the source region 104 generates hot holes that are released into the P-well 108 and then collected and trapped inside the tunnel oxide 110. This phenomenon, sometimes referred to as band bending, not only deteriorates the endurance of the cell, it also results in unpredictable erase threshold voltage over time. Additional erase threshold voltage verification circuitry are thus necessary for proper operation of the cell.
Finally, because the tunnel oxide region 110 is the same size as the channel, its capacitance is relatively larger, and thus the cell coupling capacitance is lower. Lower cell coupling capacitance requires larger program and erase voltages. Larger program and erase voltages not only lower the endurance of the cell, they also add to the circuitry as they require large pump circuits.
An improvement to the flash cell shown in FIG. 1 splits the erase voltage between the control gate 102 and the source 104. Instead of applying a high voltage to the source region 104, the control gate 102 is negatively biased with respect to the source terminal. Thus, in this embodiment, programming voltages remain the same, but during erase, a negative voltage is applied to the control gate (V.sub.CG =-V.sub.PP) while the source terminal connects to the positive power supply voltage (typically 3 to 5 volts). This allows the source junction to be the same size as the drain junction, and eliminates the high-voltage junction process requirements. However, this cell requires an additional negative pump circuit and still suffers from the hot hole injection and the resulting erratic erase threshold voltage.
Various other implementations of a single-transistor flash cell have been proposed each improving on some aspects of the cell performance, but with trade-offs in other aspects. For example, one approach that eliminates performance degradations caused by the hot hole injection, places the P-well 108 inside another N-well. This allows the P-well 108 to be biased to a positive voltage along with the source and drain regions, while the control gate is biased negatively for an erase operation. This type of flash cell, however, requires a triple well technology that is much more complex and costly to manufacture. Further, the cell still requires a negative pump circuit to bias the control gate during erase.
While there have been numerous variations on the double poly stacked gate single-transistor flash cell, there is room for improvement of the structure and design of the cell in terms of endurance, speed, reliability and cost of manufacture.